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19-0792; Rev 0; 4/07
1.62V to 3.6V Improved High-Speed LLT
General Description
The MAX13042E-MAX13045E 4-channel, bidirectional level translators provide the level shifting necessary for 100Mbps data transfer in multivoltage systems. The MAX13042E-MAX13045E are ideally suited for level translation in systems with four channels. Externally applied voltages, VCC and VL, set the logic levels on either side of the device. Logic signals present on the VL side of the device appear as a high-voltage logic signal on the VCC side of the device and vice-versa. The MAX13042E-MAX13045E operate at full speed with external drivers that source as little as 4mA output current or larger. Each input/output (I/O) channel is pulled up to V CC or V L by an internal 30A current source, allowing the MAX13042E-MAX13045E to be driven by either push-pull or open-drain drivers. The MAX13042E-MAX13045E feature an enable (EN) input that places the devices into a low-power shutdown mode when driven low. The MAX13042E-MAX13045E feature an automatic shutdown mode that disables the part when VCC is less than VL. The state of I/O VCC_ and I/O VL_ during shutdown is chosen by selecting the appropriate part version. (See the Ordering Information/ Selector Guide). The MAX13042E-MAX13045E operate with VCC voltages from +2.2V to +3.6V and VL voltages from +1.62V to +3.2V, making them ideal for data transfer between low-voltage ASIC/PLDs and higher voltage systems. The MAX13042E-MAX13045E are available in 12-bump UCSPTM (1.54mm x 2.12mm) and 14-pin TDFN (3mm x 3mm) packages, and operate over the extended -40C to +85C temperature range. o 100Mbps Guaranteed Data Rate o Four Bidirectional Channels o Enable Input o 15kV ESD Protection on I/O VCC_ Lines o +1.62V VL +3.2V and +2.2V VCC +3.6V Supply Voltage Range o 12-Bump UCSP (1.54mm x 2.12mm) and 14-Pin TDFN (3mm x 3mm) Lead-Free Packages
Features
o Compatible with 4mA Input Drivers or Larger
MAX13042E-MAX13045E
Typical Operating Circuit
+1.8V +3.3V
0.1F
1F
0.1F
VL +1.8V SYSTEM CONTROLLER EN DATA 4 GND
VCC +3.3V SYSTEM
MAX13042E- MAX13045E EN I/O VL_
I/O VCC_ 4 GND
DATA GND
Applications
CMOS Logic-Level Translation Low-Voltage ASIC Level Translation Cell Phones SPITM, MICROWIRETM Level Translation Portable POS Systems Portable Communication Devices GPS Telecommunications Equipment
UCSP is a trademark of Maxim Integrated Products, Inc. SPI is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Pin Configurations appear at end of data sheet. Ordering Information/Selector Guide continued at end of data sheet.
Ordering Information/Selector Guide
PART MAX13042EEBC+T MAX13042EETD+T PINPACKAGE 12 UCSP-12 14 TDFN-EP** I/O VL_ STATE DURING SHUTDOWN High Impedance High Impedance I/O VCC_ STATE DURING SHUTDOWN High Impedance High Impedance TOP MARK ADQ ADE PKG CODE B12-3 T1433-2
Note: All devices operate over the -40C to +85C temperature range. +Denotes a lead-free package.
*Future product--contact factory for availability. **EP = Exposed paddle. 1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
1.62V to 3.6V Improved High-Speed LLT MAX13042E-MAX13045E
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.) VCC, VL .....................................................................-0.3V to +4V I/O VCC_..................................................... -0.3V to (VCC + 0.3V) I/O VL_ ...........................................................-0.3V to (VL + 0.3V) EN.............................................................................-0.3V to +4V Short-Circuit Duration I/O VL_, I/O VCC_ to GND .......Continuous Continuous Power Dissipation (TA = +70C) 12-Bump UCSP (derate 6.5mW/C above +70C) ......519mW 14-Pin TDFN (derate 24.4mW/C above +70C) .......1951mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +2.2V to +3.6V, VL = +1.62V to +3.2V, EN = VL, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, and TA = +25C.) (Notes 1, 2)
PARAMETER POWER SUPPLIES VL Supply Range VCC Supply Range Supply Current from VCC Supply Current from VL VCC Shutdown Supply Current VL Shutdown-Mode Supply Current I/O VCC_, I/O VL_ Tri-State Leakage Current EN Input Leakage Current VL - VCC Shutdown Threshold High VL - VCC Shutdown Threshold Low I/O VCC_ Pulldown Resistance During Shutdown I/O VL_ Pulldown Resistance During Shutdown I/O VL_ Pullup Current I/O VCC_ Pullup Current I/O VL_ to I/O VCC_ DC Resistance VL VCC IQVCC IQVL ISHDN-VCC ISHDN-VL ILEAK ILEAK_EN VTH_H VTH_L RVCC_PD_SD RVL_PD_SD IVL_PU_ IVCC_PU_ I/O VCC_ = VCC, I/O VL_ = VL I/O VCC_ = VCC, I/O VL_ = VL TA = +25C, EN = GND TA = +25C, EN = GND TA = +25C, EN = VL, VCC = GND TA = +25C, EN = GND TA = +25C VCC rising (Note 3) VCC falling (Note 3) MAX13043E/MAX13045E MAX13044E/MAX13045E I/O VL_ = GND, I/O VCC_ = GND I/O VCC_ = GND, I/O VL_ = GND 0 0 10 10 20 20 3 0.1VL 0.12VL 16.5 16.5 0.1 0.1 0.1 0.1 1.62 2.2 3.2 3.6 25 10 1 1 4 2 1 0.8 0.8 23 23 65 65 V V A A A A A A V V k k A A k SYMBOL CONDITIONS MIN TYP MAX UNITS
RIOVL_IOVCC (Note 4)
2
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1.62V to 3.6V Improved High-Speed LLT
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.2V to +3.6V, VL = +1.62V to +3.2V, EN = VL, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, and TA = +25C.) (Notes 1, 2)
PARAMETER ESD PROTECTION I/O VL_, EN Human Body Model Human Body Model, CVCC = 1F I/O VCC_ IEC 61000-4-2 Air-Gap Discharge, CVCC = 1F IEC 61000-4-2 Contact Discharge, CVCC = 1F LOGIC LEVELS I/O VL_ Input-Voltage High Threshold I/O VL_ Input-Voltage Low Threshold I/O VCC_ Input-Voltage High Threshold I/O VCC_ Input-Voltage Low Threshold EN Input-Voltage-High Threshold EN Input-Voltage-Low Threshold I/O VL_ Output-Voltage High I/O VL_ Output-Voltage Low I/O VCC_ Output-Voltage High I/O VCC_ Output-Voltage Low VIHL VILL VIHC VILC VIH VIL VOHL VOLL VOHC VOLC I/O VL_ source current = 20A I/O VL_ sink current = 20A, I/O VCC_ < 0.2V I/O VCC_ source current = 20A I/O VCC_ sink current = 20A, I/O VL_ < 0.15V On falling edge On rising edge VL = 1.62V VL = 3.2V VCC = 2.2V VCC = 3.6V VL = 1.62V VL = 3.2V VCC = 2.2V VCC = 3.6V 3.5 3.5 24 11 13 9 14 10 11 9 2/3 VCC 1/3 VCC 2/3 VL 1/3 VL (Note 5) (Note 5) (Note 5) (Note 5) VL - 0.4 0.4 VCC 0.4 0.2 VL - 0.2 0.15 V V V V V V V V V V 2 15 15 8 kV kV SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX13042E-MAX13045E
RISE-/FALL-TIME ACCELERATOR STAGE Accelerator Pulse Duration VL Output Accelerator Source Impedance VCC Output Accelerator Source Impedance VL Output Accelerator Sink Impedance VCC Output Accelerator Sink Impedance ns
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3
1.62V to 3.6V Improved High-Speed LLT MAX13042E-MAX13045E
TIMING CHARACTERISTICS
(+2.2V VCC +3.6V, +1.62V VL +3.2V; CIOVL_ 15pF, CIOVCC_ 10pF; RSOURCE < 150, rise/fall time < 3ns, EN = VL, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, and TA = +25C.) (Notes 1, 2)
PARAMETER I/O VCC_ Rise Time I/O VCC_ Fall Time I/O VL_ Rise Time I/O VL_ Fall Time Propagation Delay (Driving I/O VL_) Propagation Delay (Driving I/O VCC_) Channel-to-Channel Skew Propagation Delay From I/O VL_ to I/O VCC_ after EN Propagation Delay From I/O VCC_ to I/O VL_ after EN Maximum Data Rate SYMBOL tRVCC tFVCC tRVL tFVL tPVL-VCC tPVCC-VL tSKEW tEN-VCC tEN-VL Figure 1 Figure 1 Figure 2 Figure 2 Figure 1 Figure 2 (Note 4) Figure 3 Figure 3 Push-pull operation 100 5 5 CONDITIONS MIN TYP MAX 2.5 2.5 2.5 2.5 6.5 6.5 0.7 UNITS ns ns ns ns ns ns ns s s Mbps
Note 1: All units are 100% production tested at TA = +25C. Limits over the operating temperature range are guaranteed by correlation and design and not production tested. Note 2: VL must be less than or equal to VCC during normal operation. However, VL can be greater than VCC during startup and shutdown conditions. Note 3: When VCC is below VL by more than the VL - VCC shutdown threshold, the device turns off its pullup generators and the I/Os enter their respective shutdown states. Note 4: Guaranteed by design. Note 5: Input thresholds are referenced to the boost circuit.
Typical Operating Characteristics
(VCC = 3.3V, VL = 1.8V, CIOVCC_ = 10pF, CIOVL_ = 15pF, RSOURCE = 150, data rate = 100Mbps, push-pull driver, TA = +25C, unless otherwise noted.)
VL SUPPLY CURRENT vs. VCC SUPPLY VOLTAGE (DRIVING ONE I/O VL_)
MAX13042E toc01
VL SUPPLY CURRENT vs. VL SUPPLY VOLTAGE (DRIVING ONE I/O VCC_)
VCC = 3.6V VL SUPPLY CURRENT (mA) 8
MAX13042E toc02
VCC SUPPLY CURRENT vs. VCC SUPPLY VOLTAGE (DRIVING ONE I/O VL_)
MAX13042E toc03
400 390 VL SUPPLY CURRENT (A) 380 370 360 350 340 330 320 310 300 2.2 2.4 2.6 2.8 3.0 3.2 3.4
10
15
VCC SUPPLY CURRENT (mA)
12
6 4
9
6
2
3
3.6
0 1.6 2.0 2.4 2.8 3.2 VL SUPPLY VOLTAGE (V)
0 2.2 2.4 2.6 2.8 3.0 3.2 VL SUPPLY VOLTAGE (V)
3.4 3.6
VCC SUPPLY VOLTAGE (V)
4
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1.62V to 3.6V Improved High-Speed LLT MAX13042E-MAX13045E
Typical Operating Characteristics (continued)
(VCC = 3.3V, VL = 1.8V, CIOVCC_ = 10pF, CIOVL_ = 15pF, RSOURCE = 150, data rate = 100Mbps, push-pull driver, TA = +25C, unless otherwise noted.)
VCC SUPPLY CURRENT vs. VL SUPPLY VOLTAGE (DRIVING ONE I/O VCC_)
MAX13042E toc04
SUPPLY CURRENT vs. TEMPERATURE (DRIVING ONE I/O VCC_)
MAX13042E toc05
SUPPLY CURRENT vs. TEMPERATURE (DRIVING ONE I/O VL_)
9 SUPPLY CURRENT (mA) 8 7 6 5 4 3 2 IVL IVCC
MAX13042E toc06
10 VCC = 3.6V VCC SUPPLY CURRENT (mA) 8
7 6 SUPPLY CURRENT (mA) 5 IVCC 4 IVL 3 2 1
10
6
4
2
1 0 -40 -15 10 35 TEMPERATURE (C) 60 85 -40 -15 35 10 TEMPERATURE (C) 60 85
0 1.6 2.0 2.4 2.8 VL SUPPLY VOLTAGE (V) 3.2
0
VL SUPPLY CURRENT vs. CAPACITIVE LOAD ON I/O VL_ (DRIVING ONE I/O VCC_)
MAX13042E toc07
VCC SUPPLY CURRENT vs. CAPACITIVE LOAD ON I/O VCC_ (DRIVING ONE I/O VL_)
MAX13042E toc08
RISE/FALL TIME vs. CAPACITIVE LOAD ON I/O VCC_ (DRIVING I/O VL_)
1.4 1.2 RISE/FALL TIME (ns) 1.0 0.8 0.6 0.4 0.2 0 tFVCC tRVCC
MAX13042E toc09
5000
16 14 VCC SUPPLY CURRENT (mA) 12 10 8 6 4 2
1.6
VL SUPPLY CURRENT (A)
4000
3000
2000
1000
0 10 15 20 25 30 CAPACITIVE LOAD (pF) 35 40
0 10 15 20 25 30 CAPACITIVE LOAD (pF) 35 40
10
15
20 25 30 CAPACITIVE LOAD (pF)
35
40
RISE/FALL TIME vs. CAPACITIVE LOAD ON I/O VL_ (DRIVING I/O VCC_)
MAX13042E toc10
PROPAGATION DELAY vs. CAPACITIVE LOAD ON I/O VCC_ (DRIVING I/O VL_)
MAX13042E toc11
PROPAGATION DELAY vs. CAPACITIVE LOAD ON I/O VL_ (DRIVING I/O VCC_)
4.5 PROPAGATION DELAY (ns) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 tPLH tPHL
MAX13042E toc12
3.0 2.5 RISE/FALL TIME (ns) 2.0 1.5 tFVL 1.0 0.5 0 10 15 20 25 30 CAPACITIVE LOAD (pF) 35 tRVL
5.0 4.5 PROPAGATION DELAY (ns) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 tPHL tPLH
5.0
40
10
15
20 25 30 CAPACITIVE LOAD (pF)
35
40
10
15
20
25
30
35
40
CAPACITIVE LOAD (pF)
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5
1.62V to 3.6V Improved High-Speed LLT MAX13042E-MAX13045E
Typical Operating Characteristics (continued)
(VCC = 3.3V, VL = 1.8V, CIOVCC_ = 10pF, CIOVL_ = 15pF, RSOURCE = 150, data rate = 100Mbps, push-pull driver, TA = +25C, unless otherwise noted.)
TYPICAL I/O VL_ DRIVING (FREQUENCY = 26MHz, CIOVCC_ = 40pF)
MAX1342E toc13
TYPICAL I/O VCC_ DRIVING (FREQUENCY = 26MHz, CIOVL_ = 15pF)
MAX1342E toc14
I/O VL_ 1V/div
I/O VCC_ 2V/div
I/O VCC_ 2V/div
I/O VL_ 1V/div
10ns/div
10ns/div
Pin Description
PIN UCSP A1 A2 A3 A4 TDFN 8 10 12 14 NAME I/O VCC4 I/O VCC3 I/O VCC2 I/O VCC1 FUNCTION Input/Output 4. Referenced to VCC. Input/Output 3. Referenced to VCC. Input/Output 2. Referenced to VCC. Input/Output 1. Referenced to VCC. Power-Supply Voltage, +2.2V to +3.6V. Bypass VCC to GND with a 0.1F ceramic capacitor. For full ESD protection, connect an additional 1F ceramic capacitor from VCC to GND as close to the VCC input as possible. Logic Supply Voltage, +1.62V to +3.2V. Bypass VL to GND with a 0.1F ceramic capacitor placed as close to the device as possible. Enable Input. Drive EN to GND for shutdown mode, or drive EN to VL or VCC for normal operation. Ground Input/Output 4. Referenced to VL. Input/Output 3. Referenced to VL. Input/Output 2. Referenced to VL. Input/Output 1. Referenced to VL. No Connection. Leave N.C. unconnected. Exposed Pad. Connect exposed pad to GND.
B1
9
VCC
B2 B3 B4 C1 C2 C3 C4 -- --
6 2 13 7 5 3 1 4, 11 EP
VL EN GND I/O VL4 I/O VL3 I/O VL2 I/O VL1 N.C. EP
6
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1.62V to 3.6V Improved High-Speed LLT MAX13042E-MAX13045E
Test Circuits/Timing Diagrams
VL VL EN MAX13042E-MAX13045E VL VCC 50% I/O VL_ 150 CIOVCC I/O VCC_ I/O VCC_ 10% 10% VCC I/O VL_ 50% 50% 50% VCC tRVCC tFVCC
90%
90%
tPLH tPVL-VCC = tPLH OR tPHL
tPHL
Figure 1. Push-Pull Driving I/O VL_ Test Circuit and Timing
VL VL EN MAX13042E-MAX13045E VL VCC VCC
VCC
tRVL
tFVL
I/O VCC_
50% I/O VL_ I/O VCC_ 150 CIOVL tPLH 10%
90% 50%
50% 50%
90%
10% I/O VL_ tPHL
tPVCC-VL = tPLH OR tPHL
Figure 2. Push-Pull Driving I/O VCC_ Test Circuit and Timing
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7
1.62V to 3.6V Improved High-Speed LLT MAX13042E-MAX13045E
Test Circuits/Timing Diagrams (continued)
EN VL MAX13042E- VCC I/O VCC_ I/O VL_ EN
VL
MAX13045E
SOURCE I/O VL_
t'EN-VCC
0V VL 0V
RLOAD VL VCC EN VL MAX13042E- SOURCE I/O VL_ VCC RLOAD
CIOVCC I/O VCC_ VCC / 2
VCC 0V
VL EN t"EN-VCC 0V VL 0V I/O VCC_ CIOVCC VCC / 2 VCC 0V
MAX13045E
I/O VL_ I/O VCC_
tEN-VCC IS WHICHEVER IS LARGER BETWEEN t'EN-VCC AND t"EN-VCC.
EN VL SOURCE I/O VCC_ I/O VL_ RLOAD CIOVL I/O VCC_ VCC
VL
MAX13042E- VCC MAX13045E
EN
t'EN-VL
0V VCC 0V VL
I/O VL_
VL / 2
0V
VL EN VL EN t"EN-VL 0V VCC 0V I/O VCC_ I/O VL_ CIOVL I/O VL_ VL / 2 VL 0V
VL SOURCE RLOAD
MAX13042E- VCC MAX13045E
I/O VCC_
tEN-VCC IS WHICHEVER IS LARGER BETWEEN t'EN-VCC AND t"EN-VCC.
Figure 3. Enable Test Circuit and Timing
8
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1.62V to 3.6V Improved High-Speed LLT
Functional Diagram
VL VCC
MAX13042E-MAX13045E
feature an automatic shutdown mode that disables the part when VCC is less than VL. The state of I/O VCC_ and I/O VL_ during shutdown is chosen by selecting the appropriate part version (see the Ordering Information/ Selector Guide). The MAX13042E-MAX13045E operate with VCC voltages from +2.2V to +3.6V and VL voltages from +1.62V to +3.2V. For proper operation, ensure that +2.2V V CC +3.6V, +1.62V V L V CC - 0.2V. When power is supplied to VL while VCC is missing or less than VL, the MAX13042E-MAX13045E automatically enter a lowpower mode. The devices will also enter shutdown mode when EN = 0V. This allows VCC to be disconnected and still have a known state on I/O VL_. The maximum data rate depends heavily on the load capacitance (see the Rise/Fall Time vs. Capacitive Load graphs in the Typical Operating Characteristics), output impedance of the driver, and the operating voltage range.
MAX13042E-MAX13045E
Level Translation
I/O VL1
I/O VCC1
I/O VL2
I/O VCC2
I/O VL3
I/O VCC3
Input Driver Requirements
I/O VL4 EN GND I/O VCC4
Detailed Description
The MAX13042E-MAX13045E 4-channel, bidirectional level translators provide the level shifting necessary for 100Mbps data transfer in multivoltage systems. The MAX13042E-MAX13045E are ideally suited for level translation in systems with four channels. Externally applied voltages, VCC and VL, set the logic levels on either side of the device. Logic signals present on the VL side of the device appear as a high-voltage logic signal on the VCC side of the device and vice-versa. The MAX13042E-MAX13045E operate at full speed with external drivers that source as little as 4mA output current. Each I/O channel is pulled up to VCC or VL by an internal 30A current source, allowing the MAX13042E-MAX13045E to be driven by either pushpull or open-drain drivers. The MAX13042E-MAX13045E feature an enable (EN) input that places the devices into a low-power shutdown mode when driven low. The MAX13042E-MAX13045E
The MAX13042E-MAX13045E architecture is based on an nMOS pass gate and output accelerator stages (Figure 6). The accelerators are active only when there is a rising/falling edge on a given I/O. A short pulse is then generated where the output accelerator stages become active and charge/discharge the capacitances at the I/Os. Due to its architecture, both input stages become active during the one-shot pulse. This can lead to current feeding into the external source that is driving the translator. However, this behavior helps to speed up the transition on the driven side. The MAX13042E-MAX13045E have internal current sources capable of sourcing 30A to pull up the I/O lines. These internal-pullup current sources allow the inputs to be driven with open-drain drivers as well as push-pull drivers. It is not recommended to use external pullup resistors on the I/O lines. The architecture of the MAX13042E-MAX13045E permits either side to be driven with a minimum of 4mA drivers or larger.
Output Load Requirements
The MAX13042E-MAX13045E I/O are designed to drive CMOS inputs. Do not load the I/O lines with a resistive load less than 25k and do not place an RC circuit at the input of these devices to slow down the edges. If a slower rise/fall time is required, refer to the MAX3000E/ MAX3001E logic-level translator data sheet.
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9
1.62V to 3.6V Improved High-Speed LLT MAX13042E-MAX13045E
VL ENABLE ENABLE ENABLE VCC
late signals without inversion. These devices provide the smallest solution (UCSP package) for unidirectional level translation without inversion.
ESD Test Conditions
ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results.
I/O VCC_
30A I/O VL_
30A
Use with External Pullup/ Pulldown Resistors
Due to the architecture of the MAX13042E-MAX13045E, it is not recommended to use external pullup or pulldown resistors on the bus. In certain applications, the use of external pullup or pulldown resistors is desired to have a known bus state when there is no active driver on the bus. The MAX13042E-MAX13045E include internal pullup current sources that set the bus state when the device is enabled. In shutdown mode, the state of I/O VCC_ and I/O VL_ is dependent on the selected part version (see the Ordering Information/Selector Guide).
VL BOOST CIRCUIT VL BOOST CIRCUIT
VCC
VCC
NOTE: THE MAX13042E-MAX13045E ARE ENABLED WHEN VL < VCC AND EN = VL.
Figure 4. Simplified Functional Diagram for One I/O Line
Open-Drain Signaling
The MAX13042E-MAX13045E are designed to pass opendrain as well as CMOS push-pull signals. When used with open-drain signaling, the rise time will be dominated by the interaction of the internal pullup current source and the parasitic load capacitance. The MAX13042E-MAX13045E include internal rise-time accelerators to speed up transitions, eliminating any need for external pullup resistors. For applications such as I2C or 1-wire that require an external pullup resistor, please consult the MAX3378E and MAX3396E data sheets.
Shutdown Mode
The MAX13042E-MAX13045E feature an enable (EN) input that places the devices into a low-power shutdown mode when driven low. The MAX13042E-MAX13045E feature an automatic shutdown mode that disables the part when VCC is unconnected or less than VL.
Applications Information
Layout Recommendations
Use standard high-speed layout practices when laying out a board with the MAX13042E-MAX13045E. For example, to minimize line coupling, place all other signal lines not connected to the MAX13042E- MAX13045E at least 1x the substrate height of the PCB away from the input and output lines of the MAX13042E-MAX13045E.
UCSP Applications Information
For the latest application details on UCSP construction, dimensions, tape carrier information, PCB techniques, bump-pad layout, and recommended reflow temperature profiles, as well as the latest information on reliability testing results, go to Maxim's website at www.maxim-ic.com/ucsp to find the Application Note: UCSP - A Wafer-Level ChipScale Package.
Power-Supply Decoupling
To reduce ripple and the chance of introducing data errors, bypass VL and VCC to ground with 0.1F ceramic capacitors. Place all capacitors as close to the power-supply inputs as possible. For full ESD protection, bypass VCC with a 1F ceramic capacitor located as close to the VCC input as possible.
Chip Information
PROCESS: BiCMOS
Unidirectional vs. Bidirectional Level Translator
The MAX13042E-MAX13045E bidirectional level translators can operate as a unidirectional device to trans-
10
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1.62V to 3.6V Improved High-Speed LLT
Pin Configurations
TOP VIEW TOP VIEW (BUMPS ON BOTTOM) 1 + + 14 13 12 11 10 9 *EP 8 I/O VCC1 A EN I/O VL2 N.C. I/O VL3 VL I/O VL4 2 3 4 5 6 7 GND I/O VCC2 N.C. I/O VCC3 VCC I/O VCC4 C I/O VL4 I/O VL3 I/O VL2 I/O VL1 I/O VCC4 B VCC VL EN GND I/O VCC3 I/O VCC2 I/O VCC1 2 3 4
MAX13042E-MAX13045E
I/O VL1
1
MAX13042E-MAX13045E
MAX13042E-MAX13045E
UCSP (1.54mm x 2.12mm)
TDFN (3mm x 3mm)
*CONNECT EXPOSED PAD TO GROUND
Ordering Information/Selector Guide (continued)
PART MAX13043EEBC+T MAX13043EETD+T MAX13044EETD+T* MAX13045EETD+T* PINPACKAGE 12 UCSP-12 14 TDFN-EP** 14 TDFN-EP** 14 TDFN-EP** I/O VL_ STATE DURING SHUTDOWN High Impedance High Impedance 16.5k to GND 16.5kto GND 16.5k to GND 16.5k to GND I/O VCC_ STATE DURING SHUTDOWN 16.5k to GND 16.5k to GND High Impedance High Impedance 16.5k to GND 16.5k to GND TOP MARK ADR ADF ADS ADG ADT ADH PKG CODE B12-3 T1433-2 B12-3 T1433-2 B12-3 T1433-2
MAX13044EEBC+T* 12 UCSP-12 MAX13045EEBC+T* 12 UCSP-12
Note: All devices operate over the -40C to +85C temperature range. +Denotes a lead-free package.
*Future product--contact factory for availability. **EP = Exposed paddle.
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11
1.62V to 3.6V Improved High-Speed LLT MAX13042E-MAX13045E
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 4x3 UCSP 21-0104 F
1 1
12
______________________________________________________________________________________
12L, UCSP 4x3.EPS
1.62V to 3.6V Improved High-Speed LLT MAX13042E-MAX13045E
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 6, 8, &10L, DFN THIN.EPS ______________________________________________________________________________________ 13
1.62V to 3.6V Improved High-Speed LLT MAX13042E-MAX13045E
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS SYMBOL A D E A1 L k A2 MIN. 0.70 2.90 2.90 0.00 0.20 MAX. 0.80 3.10 3.10 0.05 0.40
PACKAGE VARIATIONS PKG. CODE T633-2 T833-2 T833-3 T1033-1 T1033-2 T1433-1 T1433-2 N 6 8 8 10 10 14 14 D2 1.50-0.10 1.50-0.10 1.50-0.10 1.50-0.10 1.50-0.10 1.70-0.10 1.70-0.10 E2 2.30-0.10 2.30-0.10 2.30-0.10 2.30-0.10 2.30-0.10 2.30-0.10 2.30-0.10 e 0.95 BSC 0.65 BSC 0.65 BSC 0.50 BSC 0.50 BSC 0.40 BSC 0.40 BSC JEDEC SPEC MO229 / WEEA MO229 / WEEC MO229 / WEEC MO229 / WEED-3 MO229 / WEED-3 ------b 0.40-0.05 0.30-0.05 0.30-0.05 0.25-0.05 0.25-0.05 0.20-0.05 0.20-0.05 [(N/2)-1] x e 1.90 REF 1.95 REF 1.95 REF 2.00 REF 2.00 REF 2.40 REF 2.40 REF
0.25 MIN. 0.20 REF.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
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